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	Building Traceability between FPGA Requirements and HDL Design using Active HDL (aldecinc) View
	1.8 - Active-HDL™ (v13.1) Basics: Traceability (aldecinc) View
	Tutorial: Recognizing a bit array in Active HDL (P N) View
	Building the Traceability Bridge Highlights (RedLine Solutions Produce) View
	Generating DO-254 compliant documents for FPGA projects (aldecinc) View
	2.4 - Active-HDL™ (v13.1) Debugging: Waveform Viewer (aldecinc) View
	Aldec ALINT Demo (Ian Gibbins) View
	Import HDL for Cosimulation with Simulink (MATLAB) View
	Moving average trading model for HFT from Matlab to FPGA HDL Verilog for ultra lowest latency (Bryan Downing) View
	Breakthrough HFT Demo of Matlab Similink visual model to Coder c or c++ and HDL for FPGA (Bryan Downing) View