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	Cadence Floating Gate ISFET QRC parasitic extraction (Oleksandr Dobroliubov) View
	Quantus FS—Massively Parallel and Cloud-Ready 3D Parasitic Extraction Field Solver (Cadence Design Systems) View
	CMOS Inverter \|\| Parasitic Extraction and Post-Layout Simulation (Srisa Medicharla) View
	Cadence: Layout Extraction (ams sjsu) View
	DRC + LVS + Parasitic Extraction (Xiang Li) View
	Introduction to Physical Design of Floating-Gate Devices (Professor Jennifer Hasler's Circuit Lectures) View
	Inverter Layout \|\| DRC, LVS \|\| Parasitic Extraction \|\| 17ECL77 (Praveena K S) View
	Introduction to Floating-Gate Circuits (Professor Jennifer Hasler's Circuit Lectures) View
	Israeli HiPer Consortium N16 Tapeout with Pegasus (Cadence Design Systems) View
	Cadence Clarity 3D Transient Solver (Cadence Design Systems) View