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	Day 7: Systolic Arrays and TPU: Sparsh Mittal (HPC Education) View
	Day 7: Systolic Array: Sparsh Mittal (HPC Education) View
	Day 7: TPU Part 1: Sparsh Mittal (HPC Education) View
	Day 7: TPU Part 2: Sparsh Mittal (HPC Education) View
	Day 3: DRAMs: How Roofline Model Helps Optimizations: Sparsh Mittal (HPC Education) View
	Day 3: DRAMs: Ceilings in Roofline Model: Sparsh Mittal (HPC Education) View
	[ICCAD'20] SuSy: A Programming Model for Constructing High-Performance Systolic Arrays on FPGAs (Cornell Zhang Research Group) View
	[FPT 2019] Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit (Nachiket Kapre) View
	Systolic Array Architecture 1/2 (Lorenzo Di Tucci) (Polimi OpenKnowledge) View
	Day 3: DRAMs: Roofline Model and Arithmetic Intensity: Sparsh Mittal (HPC Education) View