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FPGA BASED DESIGN OF A NOVEL ENHANCED ERROR DETECTION AND CORRECTION TECHNIQUE (VERILOG COURSE TEAM) View |
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A Method to Design Single Error Correction Codes with Fast Decoding for a Subset of Critical Bits (Nxfee Innovation) View |
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DESIGN OF ORTHOGONAL CODE CONVOLUTION FOR ERROR DETECTION AND CORRECTION TECHNIQUE USING VERILOG HDL (VERILOG COURSE TEAM) View |
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Error Detection and Correction in SRAM Emulated TCAMs (Nxfee Innovation) View |
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DESIGN AND IMPLEMENTATION OF ORTHOGONAL CODE CONVOLUTION USING ENHANCED ERROR CONTROL TECHNIQUE (VERILOG COURSE TEAM) View |
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Fault Tolerance Methods in FPGAs (Chris Daucher) View |
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Design of SEU Tolerant 2D-FFT in SRAM-based FPGA (Nxfee Innovation) View |
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An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable... (0617) (IEEEComputerSociety) View |
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Final Year Projects | Error Detection in Majority Logic Decoding (ClickMyProject) View |
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A Novel Approach for Parallel CRC generation for high speed application (Vamsi A) View |