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	PART 1: RTL SYNTHESIS USING CADENCE GENUS TOOL (VLSI Tool Box) View
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	Verification of RTL synthesis in Cadence Genus (MD Arafat Kabir) View
	How to write TCL file for synthesis in genus/ design compiler (Anand Raj) View
	VLSI Lab, Part A, Digital Design, Basic Gates Simulation and Synthesis (Study at Home) View
	cadence simulation tutorial of digital design \| verilog code simulation in cadence tool \|VLSI design (Explore Electronics) View
	synthesis using genus tool with tcl script (Anand Raj) View