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	RTL Development with Jasper Design Automation (Jasper Design Automation) View
	RTL Block Verification with Jasper Design Automation (Jasper Design Automation) View
	Cadence Collaborates with the University of Oxford to Develop the New Jasper C2RTL App (Cadence Design Systems) View
	DAC 2012 Update on AMIQ's DVT IDE -- New RTL Design Work Flow Support (Joe Hupcey III) View
	Introduction to JasperGold Low Power Verification App (Jasper Design Automation) View
	Using Formal Technology for Security Verification of SoC Designs (Jasper Design Automation) View
	Using IP/SoC Executable Specifications and Integration with Formal Verification (Jasper Design Automation) View
	Formal Attire (Semiconductor Engineering) View
	Leveraging Formal Verification Throughout the Entire Design Cycle (Mike Bartley) View
	JasperGold RTL Designer Signoff with Superlint and CDC -- Cadence Design Systems (EE Journal) View