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	Using High Level Synthesis To Manage Power (Semiconductor Engineering) View
	Stratus™ High Level Synthesis -- Cadence (EE Journal) View
	High Level Synthesis (HLS) Explanation 6: RAMs (Dillon Huff) View
	High Level Synthesis (HLS) Explanation 4: Verilog Generation (Dillon Huff) View
	LegUp High-Level Synthesis (Jason Anderson) View
	Formal Verification of High-Level Synthesis (ACM SIGPLAN) View
	High Level Synthesis (HLS) Explanation 5: Resource Constraints (Dillon Huff) View
	Course Structure: High-Level Synthesis for FPGA, Part 1 (High Level Synthesis) View
	High Level Synthesis (HLS) Explanation 2: Scheduling (Dillon Huff) View
	Extending High-Level Synthesis with High-Performance Computing Performance Visualization (IEEEComputerSociety) View